Micro systems or hardware

A micro system includes some memory and allows limited configuration of interface pins as inputs or outputs. Software running on a small microprocessor system can implement an entire design without additional hardware, although there is a disadvantage in the fact that the processor-to-interface pin data rate requires a high ratio of instructions per interface. Micro systems, however, are ready to use and address all of the market drivers. They have been successful in many human interface, system-control applications. These software-only implementations are challenged by high-performance applications with total interface bandwidths more than a few megabits per second.

Hardware systems achieve high throughput rates. These are typically integrated by using an ASIC or field programmable logic. While high-performance requirements drive the hardware logic choice, portions of a system may require high complexity, but only modest performance. Unfortunately, complex algorithms are often difficult to implement in hardware logic and may require many gates. Thus, addressing high complexity coupled with modest performance-met through software in an embedded processor-is a significant challenge.

Embedded systems

If your designs require both a processor and high-performance, data-interface capability, systems with both hardware logic and an embedded processor are probably the answer. Partition the high-level design task into software and hardware and then select appropriate technologies and tools within each of these areas. The challenge of integrating this SOC is in combining the physical elements of the software system with the rest of the hardware blocks. Each design phase requires extensive effort. You must select a processor, design a bus, interface to all blocks, place and route all bus signals, and still meet timing constraints.

Configurable SOCs (CSOCs) already have a complete system implemented in hard logic that includes a bus extending throughout the user-configurable logic. Software development can start immediately with a complete, working, and stable physical platform. A major portion of the hardware integration is complete. You interface to the bus by defining the local configuration of some simple synchronous interface elements called selectors. These selectors are already distributed throughout the chip, providing localized bus interfaces.

At Triscend Corp. (Mountain View, CA), we've designed several families of CSOCs. The Triscend E5 and A7 families are single-chip systems with processor, memory, bus, DMA controller, and logic that may be configured and reconfigured by the user in the field. The E5 and A7's configurable system logic (CSL) contains 256 to 4096 logic cells and associated general purpose routing. Each logic cell may be used as a 4-input look-up table or for other functions such as a 16-bit memory.

All pins connect to the CSL and have various drive strength and register configuration options. Even the dedicated serial interface block can be connected to any pin via the CSL.

CSOC architecture

The processor and basic system surrounding it are implemented in hard logic. This is about 25 times more efficient in silicon than when implemented in user-configurable logic. The programs of the processors can be changed at any time since they are stored in memory.

The hard implementation provides an underlying platform that can be trusted and doesn't need to be debugged. A bus monitor generates real-time breakpoint events. This way the designer can observe and control all locations on the bus. These diagnostic features help verify and debug both hardware and software designed by the user.

Additionally. starting with an off-the-shelf system chip, fewer tools are involved in the hardware design. Standard schematic or HDL synthesis methods can be used for design entry. Standard simulation tools are used for design verification. Sections of interface logic may even be verified in hardware before the entire design is complete. Some functional blocks already exist as IP. The CSOC vendor's physical design software places and routes the design. The output of the physical design is a configuration file that is loaded into the chip to define the user's logic.

Software may be written in C or assembly and debugged on the target system. Many third-party tools are available. A simple JTAG interface provides the download and debugging access. Within the software portion, standard real-time operating systems (RTOSs) and driver interfaces may be used to provide an event driven application framework.

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